With the rapid development of semiconductor manufacturing technology, to achieve higher computing speed, larger data storage capacity and more functions, semiconductor devices have been developed toward higher device density and higher integration level. Thus, the gate of the complementary metal oxide semiconductor (CMOS) transistors has become shorter and shorter. Controlling the carrier mobility of the channel region is often used to improve the performance of the semiconductor devices. One common approach to control the carrier mobility is to control the stress in the channel region of a transistor so as to increase the drive current.
Currently, the embedded SiGe technique is often used to increase the stress in the channel region of a transistor. Specifically, SiGe material is formed in the regions for forming source/drain regions, and then a doping process is performed to form the source/drain regions. The SiGe material is used to generate a crystal lattice mismatch between silicon and the SiGe material to generate a compressive stress. The compressive stress is used to control the carrier mobility to improve the performance of the PMOS transistor.
The existing fabrication process of a PMOS transistor having SiGe source/drain regions includes providing a semiconductor substrate; forming a gate structure having a gate dielectric layer and a gate electrode on the gate dielectric layer on the semiconductor substrate; forming sidewall spacers on the side surfaces of the gate structure; forming low dose drain regions in the semiconductor substrate at two sides of the gate structure by a low dose ion implantation process using the gate structure and the sidewall spacers as a mask; forming main sidewall spacers on the surfaces of the sidewall spacers; forming trenches in the semiconductor substrate at the two sides of the gate structure by etching the semiconductor substrate using the gate structure and the main sidewall spacers as an etching mask; and filling the trenches with SiGe material; and doping the SiGe material. Thus, the SiGe source/drain regions are formed.
However, the performance of the PMOS transistors formed by the existing methods needs further improvements. For example, the carrier mobility of the channel region may need further improvements. The disclosed device structures and methods are directed to improve the performance of PMOS transistors and other problems in the art.